Intel Arrow Lake-S CPU gets delidded ahead of launch, showcasing tiled architecture
What just happened? Intel’s new Arrow Lake desktop processors are set to hit shelves later this week, but one hardware enthusiast has already managed to get an early look under the hood. Streamer Madness727 got their hands on an upcoming Core Ultra Arrow Lake-S model and did the unthinkable – he delidded it.
The delidding process involves removing the integrated heat spreader (IHS) from the top of the CPU. It’s a risky move that can damage the chip if not done correctly, but it allows for direct cooling of the silicon dies inside, which is something hardcore overclockers love for pushing performance to the limit. Of course, it also voids your warranty.
Madness727 shared multiple photos of the delidded Arrow Lake-S chip, giving us the first real-world look at the novel chiplet design Intel is using for this new generation. While the specific model remains unidentified, this isn’t particularly important, as all Arrow Lake-S models share the same tile configuration.
At the center, you’ve got the big compute tile packing those 8 performance (Lion Cove) and 16 efficiency (Skymont) cores we’ve heard so much about. Flanking it is the graphics tile with 4 Xe GPU cores embedded. Then there are the obligatory I/O tile that integrates a Thunderbolt 4 controller, and SoC tile handling other chipset functions.
I just can’t stop myself from delidding stuff pic.twitter.com/XmniBHY5U8
– Madness! (@Madness727) October 18, 2024
Interestingly, there’s also a vacant “dummy” tile that seems to just be there for structural support.
For the uninitiated, a chiplet design with its tiled architecture allows Intel to mix-and-match different tiles using optimized process nodes for better performance-per-watt. It also makes it easier to swap in cutting-edge components each generation without overhauling the entire CPU design.
Also read: What Are Chiplets and Why They Are So Important for the Future of Processors
Case in point, Arrow Lake-S uses different process nodes for various components. The compute tile, which houses the cores, is built on TSMC’s advanced N3B node, while the GPU tile uses N5P, and the SoC and I/O tiles are based on the more mature N6 process. Remarkably, all five tiles are assembled on a base layer fabricated using Intel’s 22nm FinFET technology.
While the desktop Arrow Lake-S models utilize this 5-tile layout, Intel’s mobile “Arrow Lake-H” chips headed for laptops in Q1 2025 will rock a more stripped-down configuration. These mobile CPUs will feature a smaller compute tile with a 6P+8E core complex, an expanded graphics tile with 8 Xe cores, and a reduced I/O tile.
